Inverted Staggered Poly-Si Thin-Film Transistor With Planarized SOG Gate Insulator

Abstract

In this letter, we have studied the inverted staggered thin-film transistor (TFT) using a spin-on-glass (SOG) gate insulator and a low-temperature polycrystalline silicon (poly-Si) by Ni-mediated crystallization of amorphous silicon. The p-channel poly-Si TFT exhibited a field-effect mobility of 48.2 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V ldr s, a threshold voltage of -4.2 V, a gate-voltage swing of 1.2 V/dec, and a minimum off-current of < 4 times 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-13</sup> A/ mum at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</sub> = -0.1 V. Therefore, the gate planarization technology by SOG can be applicable to low-cost large-area poly-Si active-matrix displays.