A bist solution for the test of I/O speed

Abstract

A delay-locked loop (DLL) based built-in self test (BIST) circuit has been designed with a 0.18 p m TSMC process (CM018) to test chip I/O speeds, specijkally, the setup and hold times of I10 registers or buffers. The frequency lock range of the DLL is 150-600 MHz (4x). The DLL uses a combined phase detector and charge pump circuit (PD+CP) for increased speed and reduced jitter. The DLL also employs an eight-stage shift averaging voltagecontrolled delay line (VCDL) to improve the matching between delay stages and thus to equalize the delay of each individual stage. The locking failure or false locking problems are alleviated by using a start-control circuit. setup and hold times are two of the key metrics to evaluate the register or buffer's AC electrical characteristics. Therefore, it is important to test the specifications on setup and hold times. These tests will fail if the delays from the data inputs to the registers and from the clock input to the registers differ such that the data is not valid before (setup time) and after (hold time) the clock is asserted. This may happen due to delays in long buffered interconnect lines and in the clock tree. In order to satisfy the timing requirements, the delay in the clock tree must be larger than the delay for the data input by the setup time requirement, but not so large as to violate the hold time requirement.