2003 · 48 citations · 3 references
EngineeringElectrical EngineeringComputer ArchitectureMicroelectronicsSemiconductor DevicesClock Distribution NetworksClock ManagementCmos Circuit DesignDigital Integrated Circuit DesignMixed-signal Integrated Circuit DesignTiming AnalysisClock DesignClock DistributionCmos Logic CircuitsDynamic Cmos LogicDynamic LogicHigh-speed Cmos DesignHigh-speed OperationRise Time
Some CMOS circuit techniques, based on a true single-phase clock, where the clock is never inverted, are described. Single-phase dynamic logic and single-phase precharge logic circuits are considered. The advantage of this approach is simple and compact clock distribution and high speed. The high-speed possibility was demonstrated with a binary divider. A clock frequency of 160 MHz was achieved when only standard transistors in a 3- mu m CMOS process were used. The single-phase clock is relatively insensitive to clock rise time, clock fall time, and clock skew.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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