Vertically Stacked Silicon Nanowire Transistors Fabricated by Inductive Plasma Etching and Stress-Limited Oxidation

Abstract

A simple top-down method for realizing an array of vertically stacked nanowires is presented. The process utilizes the nonuniformity in inductively coupled plasma (ICP) etching to form a scallop pattern at the sidewall of a tall silicon ridge that is further trimmed to form stacked nanowires by stress-limited oxidation. The process has been demonstrated to be controllable and repeatable, starting with bulk silicon wafers. Vertically stacked gate-all-around MOSFETs have been fabricated, which show excellent performance with a nearly ideal subthreshold slope of 62 mV/dec, a low leakage current, and a high <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> / <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> ratio of ~ 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8</sup> .