2001 · 29 citations · 19 references
EngineeringComputer EngineeringComputer ScienceFault-tolerant ComputingFault-tolerant SystemsField-programmable Gate ArraysConfigurable Logic BlocksConfiguration MemoryField-programmable Gate Array ArchitectureFpga ArchitectureLookup TablesPartial ReconfigurationCoherence OptimizationConfigurable Logic Block DesignExecution Time AnalysisField-programmable Gate Arrays (Fpgas)Memory CoherencePartial Reconfiguration ArchitectureReconfigurable Logic BlocksReconfiguration Of Field-programmable Gate Arrays
The partial reconfiguration feature of some of the current-generation Field Programmable Gate Arrays (FPGAs) can improve dependability by detecting and correcting errors in on-chip configuration data. Such an error recovery process can be executed online with minimal interference of user applications. However, because Look-up Tables (LUTs) in Configurable Logic Blocks (CLBs) of FPGAs can also implement memory modules for user applications, a memory coherence issue arises such that memory contents in user applications may be altered by the online configuration data recovery process. In this paper, we investigate this memory coherence problem and propose a memory coherence technique that does not impose extra constraints on the placement of memory-configured LUTs. Theoretical analyses and simulation results show that the proposed technique guarantees the memory coherence with a very small (on the order of 0.1%) execution time overhead in user applications.
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Which concurrent error detection scheme to choose ?
Subhasish Mitra, E.J. McCluskey · 2002 · 296 citations