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A low-overhead coherence solution for multiprocessors with private cache memories
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1998
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EngineeringComputer ArchitectureMemory Model (Programming)Processor ArchitectureHardware SystemsMulti-channel Memory ArchitectureAlertsnew Citation AlertHardware SecurityShared MemoryHigh-performance ArchitectureComputing SystemsParallel ComputingData ManagementPrivate Cache MemoriesAccount SaveComputer EngineeringComputer ScienceMemory ArchitectureTheory Of ComputingAlert PreferencesMultiprocessor SystemParallel ProgrammingAsynchronous Systems
Article Free AccessA low-overhead coherence solution for multiprocessors with private cache memories Share on Authors: Mark S. Papamarcos Coordinated Science Laboratory, University of Illinois, 1101 W. Springfield, Urbana, IL Coordinated Science Laboratory, University of Illinois, 1101 W. Springfield, Urbana, ILView Profile , Janak H. Patel Coordinated Science Laboratory, University of Illinois, 1101 W. Springfield, Urbana, IL Coordinated Science Laboratory, University of Illinois, 1101 W. Springfield, Urbana, ILView Profile Authors Info & Claims ISCA '98: 25 years of the international symposia on Computer architecture (selected papers)August 1998 Pages 284–290https://doi.org/10.1145/285930.285987Online:01 August 1998Publication History 11citation583DownloadsMetricsTotal Citations11Total Downloads583Last 12 Months11Last 6 weeks4 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF
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