A zero-IF 60GHz transceiver in 65nm CMOS with ≫ 3.5Gb/s links

Abstract

This paper presents a 1.2 V 60 GHz zero-IF transceiver fabricated in a 65 nm CMOS process with a digital back-end. The chip includes a receiver with 14.7 dB gain, a low 5.6 dB noise figure, a 60 GHz LO distribution tree, a 64 GHz static frequency divider, and a direct BPSK modulator operating over the 55-65 GHz band at data rates exceeding 3.5 Gb/s. The chip consumes 374 mW (232 mW) from 1.2 V (1.0 V) and occupies 1.28 times 0.81 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The transceiver was characterized over temperature up to 85degC and for power supplies down to 1 V. A manufacturability study of 60 GHz radio circuits is presented with measurements of transistors, the low-noise amplifier, and the receiver on typical and fast process splits. The transceiver performance is demonstrated using a 3.5 Gb/s 2-meter wireless transmit-receive link over the 55-64 GHz range.