Defect-oriented vs schematic-level based fault simulation for mixed-signal ICs

TLDR

The growing demand for mixed‑signal ICs drives the need for efficient production testing and Design‑for‑Testability to achieve higher quality at lower cost, with fault simulation playing a key role in evaluating test effectiveness. The study compares two fault‑list generation methods to assess their impact on test optimization. The authors compare fault lists from Inductive Fault Analysis and a transistor fault model in a testability analysis of a self‑test function for a high‑performance switched‑current design.

Abstract

Escalating demand for mixed-signal Integrated Circuits has been accompanied by the need to develop efficient strategies to guarantee higher quality at lower cost. One key to achieving this is efficient production test and the utilization of Design-for-Testability (DfT). Fault simulation based test evaluation would be a major contribution towards measuring and optimizing the effectiveness of a production test. Fault simulations, however, are only useful if the underlying fault list generation approaches accurately reflect manufacturing defects-both in their probability of occurrence and in their electrical behavior. This paper evaluates and compares two fault list generation approaches and the implications on test optimization. Fault lists derived from both Inductive Fault Analysis (IFA) and a transistor fault-model are compared for a testability analysis on a self-test function for a high-performance switched-current design.