1994 · 21 citations · 17 references
ComputingComputer EngineeringComputer ScienceCompilersComputer ArchitectureProgramming LanguagesCache CoherenceCachingControl-flow AnalysisData-flow AnalysisShared-memory MultiprocessingShared-memory ParallelismCache Coherence ProtocolsCache CoherencyCoherence ProtocolsCompiler DesignInterprocedural Dataflow AnalysisLive Variable AnalysisShared MemoryShared Memory Multiprocessors
We study in this paper the design and efficiency of compiler algorithms that remove ownership overhead in shared-memory multiprocessors with write-invalidate protocols. These algorithms detect loads followed by stores to the same address. Such loads are marked and constitute a hint to the cache to obtain an exclusive copy of the block. We consider three algorithms where the first one focuses on load-store sequences within each basic block of code and the other two analyse the existence of load-store sequences across basic blocks at the intra-procedural level. Since the dataflow analysis we adopt is a trivial variation of live-variable analysis, the algorithms are easily incorporated into a compiler.
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The Stanford Dash multiprocessor
Daniel Lenoski, James Laudon, Kourosh Gharachorloo et al. · Computer · 1992 · 972 citations
Jaswinder Singh, Wolf-Dietrich Weber, Anoop Gupta · ACM SIGARCH Computer Architecture News · 1992 · 927 citations · Full text
Design and evaluation of a compiler algorithm for prefetching
Todd C. Mowry, Monica S. Lam, Anoop Gupta · 1992 · 767 citations · Full text