Design and evaluation of a compiler algorithm for prefetching

Abstract

Software-controlled data prefetching is a promising technique for improving the performance of the memory subsystem to match today's high-performance processors. While prefctching is useful in hiding the latency, issuing prefetches incurs an instruction overhead and can increase the load on the memory subsystem. As a resu 1c are must be taken to ensure that such overheads do not exceed the benefits.