VHDL implementation of fast NxN multiplier based on vedic mathematic

Abstract

A novel technique for digital multiplication is presented that is quite different from the conventional method of multiplication like add and shift (D. Crawley and G. Amaratunga, 1996). This also gives chances for modular design where smaller block can be used to design the bigger one. This will help in designing multiplier in VHDL, as its give effective utilization of structural method of modeling (Hwang Kai, 1979). In this paper the general technique for NxN multiplication is proposed. This gives less computation time for calculating the multiplication result for NxN bit.