Semi-formal verification of VHDL-AMS descriptions

Abstract

In this paper a new technique for functional verification of VHDL-AMS descriptions is proposed. The technique is based on combining an equivalence checker, an analog simulator, and a term rewriting engine in a single tightly coupled verification environment. The proposed method verifies the equivalence between two VHDL-AMS architectures describing alternative implementations or different abstraction levels for the same A/MS design entity. The verification process is based on building comparator circuits for the analog outputs and miter circuits for the digital outputs. The miter circuit is verified using a novel SAT/BDD equivalence checking algorithm. The analog comparator circuit is verified using a set of rewriting rules. The equivalence of D/A & A/D converters is proved using a matching procedure.