Semi-formal verification is a methodological approach within formal methods that combines rigorous, mathematically-inspired techniques with less formal, simulation-based or assertion-driven methods to validate system properties. This research concept investigates the correctness of complex hardware and software designs by employing techniques such as assertion-based verification, constrained random simulation, and targeted model checking or theorem proving on specific aspects or scenarios. Its key characteristics include balancing the exhaustive guarantees of full formal verification with the scalability and practicality of simulation, focusing on proving properties under specified conditions rather than exploring the entire state space. The significance of semi-formal verification lies in its ability to provide a more rigorous alternative to traditional simulation for large-scale systems, enhancing confidence in design integrity where full formal methods are computationally prohibitive.