Reduction of Leakage by Implantation Gettering in VLSI Circuits

Abstract

Damage introduced by ion implantation on the back side of the wafer is used to reduce the MOS transient (relaxation) and junction leakage; the technique is applied to dynamic memory cells. Conditions necessary to ensure efficient gettering by various species (B, Ar, Kr, and Xe) are established based on achieving a sufficient density of b = ½ 〈110〉 dislocations. When the implantation occurs through a screen oxide, dose levels of less than 3 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">14</sup> ions/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> for Ar were found to be suitable. Equivalent leakage reduction was obtained for all species. Specifically, B at 5 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">15</sup> ions/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> was as effective in reducing relaxation leakage as was 1 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">15</sup> ions/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> of Ar for the particular thermal history of the investigated process.