A 64 bit carry look-ahead CMOS adder using Modified Carry Select

Abstract

We present a 64 b Carry Look-ahead (CLA) adder having a 2.6 ns delay time at 3.3 V power supply within 0.27 mm/sup 2/ using a 0.5 /spl mu/m CMOS technology. We derived its structure from considering the tradeoffs between speed and area. This consideration includes not only the gate intrinsic delay but also the wiring delay and the gate capacitance delay. Moreover we introduced a new carry select scheme called Modified Carry Select (MCS). MCS has 20% area advantage over the conventional Carry Select Adder (CSA).