IEEE Transactions on Computers · 1992 · 47 citations · 21 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureField-programmable Gate ArraysMicroelectronicsArray ProcessingClock ManagementTiming AnalysisAsynchronous ProcessingComplexitySystolic Array DesignSystolic ArraysThroughput
An approach is presented to high-performance asynchronous architectures offering significant advantages over conventional clocked systems, without some of the drawbacks normally associated with asynchronous techniques. As the level of integration increases, an asynchronous wavefront array designed using the techniques described will have three important advantages over the equivalent synchronous systolic array: faster throughput (rate at which data are clocked through a system), reduced design complexity, and greater reliability. The benefits and drawbacks of using the asynchronous technique are highlighted using three wavefront arrays: two one-dimensional multipliers, and a two-dimensional sorter. All three can be built using just one basic building block.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
21
Sorting networks and their applications
Kenneth E. Batcher · 1968 · 2.4K citations
Ivan E. Sutherland · Communications of the ACM · 1989 · 1K citations · Full text
High-speed CMOS circuit technique
Jiren Yuan, C. Svensson · IEEE Journal of Solid-State Circuits · 1989 · 792 citations
Engineering, Computer Engineering, Electrical Engineering +16