A 50MS/s 9.9mW pipelined ADC with 58dB SNDR in 0.18µm CMOS using capacitive charge-pumps

Abstract

In the interest of extending battery life in mobile systems that use pipelined ADCs, several power-efficient pipelined ADCs have recently been proposed. The most promising topologies reported thus far are those that substitute the opamp, which is the largest consumer of power in pipelined ADCs, with alternative and more power-efficient circuits. However, opamp-less pipelined ADCs thus far either: 1) require complex nonlinear calibration, 2) are single- ended, 3) are pseudo-differential, or 4) require a sampling scheme that limits linearity (less than 8b ENOB). In this paper, a low-power pipelined ADC is presented that has significantly lower power consumption than many previous 10b ADCs in the mid-to-high speed range. The ADC does not require power-hungry opamps, and hence achieves similar power savings. However, unlike prior opamp-free topologies, the ADC: 1) requires only stage-gain digital calibration, 2) uses fully differential pipelined stages, and 3) uses a sampling scheme that can achieve high linearity (SFDR of 66dB and better than 9b ENOB).