A 9.4-bit, 50-MS/s, 1.44-mW pipelined ADC using dynamic residue amplification

Abstract

An ultra-low power pipelined ADC is realized by replacing conventional op-amp circuits with dynamic source-follower gain stages. The presented 90-nm CMOS converter operates at 50 MS/s and achieves an SNDR of 49.4 dB while dissipating 1.44 mW from a 1.2-V supply.