N^-source/drain compensation effects in submicrometer LDD MOS devices

Abstract

N- source/drain compensation effects in LDD devices and p-n junction leakage effects are investigated. In particular, for <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L_{eff} \leq 0.3</tex> µm, these effects will become intrinsic constraints on device minituarization. Furthermore, p-n junction leakage was found to cause refresh failures in dynamic VLSI circuits even under reduced power supply voltage.