Lateral smart-discrete process and devices based on thin-layer silicon-on-insulator

Abstract

A ten-mask lateral smart-discrete process technology which combines novel high-voltage RESURF transistor structures and a merged bipolar/DMOS process flow on thin-layer SOI substrates is presented. Benchmarking shows that 650 V/1.2 Ohm SOI lateral smart-discrete devices exhibit a total gate charge which is a factor-of-two lower than vertical super-junction devices, a temperature-independent body diode reverse recovery time which is a factor-of-two smaller than vertical ultra-fast silicon diodes, and total hard-switching losses which are lower than conventional VDMOS. The total gate charge, reverse recovery time, and switching delay times are the lowest reported values for 650 V silicon devices. This, in conjunction with a process with integrated logic, establishes SOI smart-discrete technology as best-in-class for efficient high-frequency power conversion.