2003 · 21 citations · 9 references
EngineeringElectrical EngineeringMicroelectronicsMicrowave EngineeringSemiconductor DevicesCmos Circuit DesignHigh-frequency Semiconductor DevicesIntegrated Circuit DesignInterconnect TechnologyMicrowave Integrated CircuitsRadio-frequency Integrated CircuitsCmos Radio-frequency CircuitsCopper InterconnectsInductor DesignInductorsInterconnect ParasiticsParasitic CapacitanceParasitic Capacitance ReductionRadio-frequency Integrated Circuit Design
Design of super compact on-chip inductors with deep-shrunk dimension of 22/spl mu/m/spl times/23/spl mu/m, as opposed to several hundreds /spl mu/m by several hundreds /spl mu/m, is reported. Implemented in a 6-metal all-copper 0.18/spl mu/m CMOS process, a flat inductor value of 10nH up to 4GHz, satisfactory to many typical RFIC applications, is achieved. The aggressive shrinkage reduces parasitic capacitance substantially and makes it realistic and cost-effective to realize single-chip RFICs in very deep sub-micron technologies. A new inductor model is proposed for accuracy. A 2.4GHz LNA circuit with on-chip matching using the compact inductor is demonstrated.
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Simple accurate expressions for planar spiral inductances
S.S. Mohan, M. del Mar Hershenson, Stephen Boyd et al. · IEEE Journal of Solid-State Circuits · 1999 · 1.6K citations