Modeling, simulation, and measurement of mid-frequency simultaneous switching noise in computer systems

TLDR

CMOS microprocessors operating at hundreds of megahertz generate large current spikes from switching activity and produce a mid‑frequency noise component lasting 50–200 ns. This work aims to design IBM’s CMOS S/390 computer to control that mid‑frequency noise. The design incorporates a 10‑way multiprocessor on a 127 mm × 127 mm multichip module on FR4, with power‑distribution and decoupling capacitors engineered to supply the tens‑of‑amp current steps without voltage disturbance. The MCM chips generate current steps of tens of amps over several cycles that persist for many cycles, and the proposed power‑distribution design successfully models and verifies mitigation of the mid‑frequency noise.

Abstract

Complementary metal-oxide-semiconductor (CMOS) microprocessors operating in the hundreds of megahertz create significant current deltas due to the variation in switching activity front clock cycle to clock cycle. In addition to the high-frequency voltage variations more commonly discussed, a lower frequency noise component is also produced that lasts from 50-200 ns which we refer to as mid-frequency noise. In this paper, we discuss the design of IBM's CMOS S/390 computer for control of mid-frequency noise. This machine has a 10-way multiprocessor on a 127 mm by 127 mm multichip module (MCM) on a FR4 board. The chips on the MCM cause a current step of tens of Amps in a few cycles that can be sustained for many cycles. The power distribution and decoupling capacitors must supply that current without disturbing the voltage level at the circuits. The design of the system power distribution and modeling and verification of mid-frequency noise in this system is presented.