Cu/Low-$k$ Interconnect Technology Design and Benchmarking for Future Technology Nodes

Abstract

This paper investigates the performances of conventional Cu/low- k multilevel interconnect networks (MINs) for FinFETs at the 20-, 16-, 14-, 10-, and 7-nm technology nodes corresponding to the even years between 2012 and 2020, respectively. This paper captures the impacts of interconnect variables, such as size effect parameters, barrier/liner bilayer thickness, and aspect ratio on the design and performance of the MIN of a logic core. The number of metal levels for a high-performance chip increases by as large as 34% due to size effects, and this value can go up to 76% considering issues in barrier/liner thickness scaling at the 7-nm technology node. At this node, increasing the aspect ratio of interconnects from two to three can improve wire delay and save two metal levels at the cost of 35% more power dissipation. A ±20% wire-width variation induces wire delay variations of -20% and 44% at minimum-width wires. Designing the MIN considering this variation increases the required wire area by 4% in the worst case.