Publication | Closed Access
Two CMOS memory cells suitable for the design of SEU-tolerant VLSI circuits
80
Citations
5
References
1994
Year
Electrical EngineeringEngineeringVlsi DesignCmos Memory CellsSeu-tolerant Vlsi CircuitsVlsi ArchitectureEmerging Memory TechnologyPrototype ChipComputer EngineeringSeu TestsMemory DevicesSemiconductor MemoryVlsiIntegrated CircuitsHit CellsMicroelectronicsHardware SystemsMemory Architecture
Two new CMOS memory cells, called HIT cells, designed to be SEU-immune are presented. Compared to previously reported design hardened solutions, the HIT cells feature better electrical performances and consume less silicon area. SEU tests performed on a prototype chip prove the efficiency of the approach.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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