Implanted silicon JFET on completely depleted high-resistivity devices

Abstract

To satisfy the increasing interest in the integration of electronics onto optical and ionizing particle fully depleted detectors, a nonconventional JFET (junction field-effect transistor), designed to operate on a completely depleted, 2-k Omega -cm resistivity silicon substrate, has been designed, fabricated, and tested at room temperature. The devices show very low gate leakage current, low output conductance, a transconductance per unit gate width of 3 mS/mm, and a pinch-off voltage of -1.5 V. The integration of the devices onto the detectors makes possible the matching of the input capacitance of the JFET to the detector's output capacitance, which is of the order of few hundreds of femtorads. The measured gate capacitance of 200 fF is shown to correspond to an expected resolution in charge measurements, at room temperature, of less than 40 electrons rms. The fabrication constraints, imposed by the limited number of production steps of the detectors, are reported.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>