The origination and optimization of Si/SiO₂ interface roughness and its effect on CMOS performance

Abstract

As CMOS device dimensions scale down to 100 nm and beyond, the interface roughness between Si and SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> has become critical to device performance and reliability. Si/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> interface roughness degrades channel mobility decreasing drive currents. The authors have used atomic force microscopy to study surface roughness in the processing of 0.16 μm CMOS integrated circuits. All of the process steps that could potentially affect the interface roughness have been studied. The results show that oxidation is the major contributor to the interface roughness. The rms roughness is found to be linearly dependent on oxide thickness. Transistors with Si/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> interface rms roughness that has been reduced from 1.6 to 1.1 /spl Aring/ by reducing oxide thicknesses show improved device drive currents. This technique for interfacial smoothing and device performance improvement has the advantage of being easily implemented in today's technology.