Bias temperature instability in scaled p/sup +/ polysilicon gate p-MOSFET's

Abstract

The bias temperature instability in surface-channel p/sup +/ polysilicon gate p-MOSFETs was evaluated. It was found that a large negative threshold voltage shift (/spl Delta/V/sub th,BT/) is induced by negative bias temperature (BT) stress in short-channel p/sup +/ polysilicon gate p-MOSFETs. This Vth shift, which depends on the gate length of p-MOSFETs, is a new degradation mode. In this degradation, the negative /spl Delta/V/sub th,BT/ increases significantly with a reduction in the gate length. It was shown that this is because of the local degradation of the gate oxide near the gate edge. This degradation is caused by the electrochemical reaction between holes and oxide defects and it is enhanced by boron penetration through the gate oxide from p/sup +/-gate. For the bias temperature instability in p/sup +/-gate p-MOSFETs, sufficient care should be taken in scaled dual-gate CMOS devices.