2011 · 19 citations · 4 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsSemiconductor DevicesCmos Circuit DesignDevice ScalingIntegrated Circuit DesignInterconnect DesignPhysical DesignPower OptimizationCmos ScalingCore Design OptimizationDevice OptimizationLow-power Cmos DesignMetal Gate ScalingProcess Design OptimizationScaling Effects In CmosTechnology Scaling
An industry leading 28nm high-performance mobile SoC technology featuring metal-gate/high-k process is presented. The technology is optimized to offer wide power-to-performance transistor dynamic range and highest wired gate density with superior low-R/ELK interconnects, critical for next generation mobile computing/SOC applications. Through process and design optimization, historical trend is maintained for gate density and SRAM cell sizes. Variations control strategy through process and design collaboration is also described.
4
45nm high-k + metal gate strain-enhanced CMOS transistors
C. Auth · 2008 · 48 citations
Engineering, Computer Engineering, Electrical Engineering +17