IEEE International Symposium on Power Semiconductor Devices and ICs/Proceedings of the International Symposium on Power Semiconductor Devices & ICs/Proceedings of the ... International Symposium on Power Semiconductor Devices & ICs/Proceedings of the ... International Symposium on Power Semiconductor Devices and ICs · 2009 · 10 citations · 2 references
EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesVlsi DesignCmos Circuit DesignComplementary Metal-oxide-semiconductor TechnologyIntegrated Circuit DesignMetal-oxide-semiconductor Field-effect TransistorsShort-channel EffectsWide-bandgap Semiconductor DevicesCmos Analog Circuit DesignCmos Analog Integrated CircuitsComplementary Metal-oxide-semiconductor DesignLeakage Current Reduction
We present a new advanced 0.18 um BCD(Bipolar-CMOS-DMOS) technology with the key features being a 40 V HV-MOS and an SSTC(Sidewall Selective Transistor Cell) type EEPROM as well as complimentary available analog devices such as a high gain BJT, 4fF/um <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> MIM capacitor, and 10k Omega/sq. poly resistor. To reduce device area and enhance latch up immunity, a 15 um depth deep trench isolation process has been developed, which will help to significantly reduce the chip size.
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BD180 - a new 0.18 μm BCD (Bipolar-CMOS-DMOS) Technology from 7V to 60V
Il-Yong Park, Yong-Keon Choi, Kwang-Young Ko et al. · 2008 · 32 citations