Metastability in CMOS library elements in reduced supply and technology scaled applications

Abstract

This paper characterizes the effects of loading, power supply, and technology scaling on the metastable parameters of CMOS latches used as synchronizers. Results from 2 /spl mu/ and 1.2 /spl mu/ test chips designed to measure the performance of buffered and unbuffered CMOS latches with respect to loading and supply voltages are presented. While the optimum synchronizer in CMOS technology has been previously shown to be an unbuffered, unloaded latch, our results show that buffered latches have better mean time between failure (MTBF) performance for all loads greater than a fanout of one with sufficient resolution time. However, MTBF performance still degrades exponentially with loading in buffered latches. A normalization scheme to compare latches with different supplies and technologies is presented with data from the test chips. Improvements in latch metastable parameters with increased supply or reduced channel length are shown to be reduced when the effects of shorter on-chip delays are factored in. In a given technology, normalized metastable parameters are shown to be unchanged for a wide range of supply voltages, allowing calculation of metastable parameters in supply voltages not explicitly measured.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>