Design of Si/SiGe heterojunction complementary metal-oxide-semiconductor transistors

Abstract

A design is presented and computer-simulated for high-mobility Si/SiGe heterojunction CMOS transistors. Comparing 0.2 /spl mu/m Si/SiGe FETs to bulk Si FETs, an increase is predicted in current drive of 125% and 23% in the p-FET and n-FET, respectively. For given propagation delay (55 ns), simulated loaded ring oscillators at 1.5 V exhibit 4.6 times reduction in power-delay-product compared to bulk Si CMOS oscillators of the same design rules operating at 2.5 V.