IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications · 2005 · 157 citations · 11 references
EngineeringComputer EngineeringElectrical EngineeringAnalog ElectronicsLow-power DesignMicroelectronicsAnalog Integrated CircuitsAnalog IntegrationCmos Circuit DesignDigital Image ProcessingImage ProcessingImage SensorsCmos Analog Circuit DesignCmos Analog Integrated CircuitsDynamic Power DissipationImage Processing UnitsImage Sensor TechnologyReal-time ProcessingSiliconVlsi Implementation
A smart-sensor VLSI circuit suitable for focal-plane low-level image processing applications is presented. The architecture of the device is based on a fine-grain software-programmable SIMD processor array. Processing elements, integrated within each pixel of the imager, are implemented utilising a switched-current analog microprocessor concept. This allows the achievement of real-time image processing speeds with high efficiency in terms of silicon area and power dissipation. The prototype 21 /spl times/ 21 vision chip is fabricated in a 0.6 /spl mu/m CMOS technology and achieves a cell size of 98.6 /spl mu/m /spl times/ 98.6 /spl mu/m. It executes over 1.1 giga instructions per second (GIPS) while dissipating under 40 mW of power. The architecture, circuit design and experimental results are presented in this paper.
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A CMOS vision chip with SIMD processing element array for 1 ms image processing
Masatoshi Ishikawa, K. Ogawa, Takashi Komuro et al. · 2003 · 116 citations