S ² I: a switched-current technique for high performance

Abstract

A new switched-current memory cell is presented which enhances basic cell performance through successive refinement of the memorised sample. This is achieved in a two-step technique, called S2I, in which the input sample is coarsely memorised, a process which introduces a combination of all the normal errors, followed by detection and suppression of the combined errors. The circuit solution requires the addition to the basic memory cell of only extra switches and so carries few of the penalties associated with alternative techniques.