Embedded interconnect and electrical isolation for high-aspect-ratio, SOI inertial instruments

Abstract

A new technique for providing both electrical isolation and embedded interconnect to SOI-based, single crystal silicon, inertial sensors is described. This technology allows fabrication of high-aspect-ratio, in-plane, capacitive sensors with improved sensitivity suitable for integration with on-chip electronics. Various 45 /spl mu/m-tall MEMS devices with electrical isolation from the silicon substrate and embedded interconnect have been fabricated and tested. The embedded interconnect and electrical isolation enable truly integrated high-aspect-ratio MEMS sensors, and alternatively simplifies packaging in monolithic two-chip approaches. By extending the demonstrated technique to aluminum interconnect, only two additional masks are required to convert a CMOS process into a fully integrated MEMS technology at the incremental cost of an SOI starting material.