Rapid single flux quantum (RSFQ) shift register family

Abstract

The author presents the design and test results for a novel, buffered RSFQ shift register. The register design makes it possible to build a circular 64-b shift register which is insensitive to the clock pulse direction within the experimentally measured DC bias margin of +or-15%. The implementation of a large variety of unidirectional shift registers using either a buffered or a two-Josephson-junction cell design confirms an expected wide DC bias margin of +or-30% (for a 32-b) and high speed, up to 60 GHz (for a 4-b register). Among these circuits is a 256-b shift register. To the author's knowledge, this is the largest RSFQ circuit (533 junctions) reported to date. This shift register was tested to have a DC bias margin of +or-6% and proper high-speed operation up to 12 GHz.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>