IEEE Transactions on Signal Processing · 1991 · 33 citations · 6 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureField-programmable Gate ArraysMicroelectronicsClock ManagementDigital Integrated Circuit DesignDigital Integrated CircuitsDigital Signal ProcessingField-programmable Gate Array ArchitectureTiming AnalysisDigital Filtering ArchitecturesFilter OrderFinite Impulse Response FiltersImpulse ResponseInfinite Impulse Response FiltersSystolic Array DesignSystolic ArraysTiming Error Analysis
An improved systolic architecture for two-dimensional infinite-impulse response (IIR) and finite-impulse-response (FIR) digital filters is presented. Comparisons with recently published work are made. When compared with the architecture of M.A. Sid-Ahmed (1989), a substantial reduction in the number of delay elements is observed. This reduction is of the order of 10/sup 2/ for a 2-D IIR filter and equals N+1 for an Nth-order 2-D FIR filter. The clock period has been made independent of the order of the filter. The speed-up factor is the maximum achievable and is independent of the filter order. Comparison with the work of S. Sunder et al. (1990) shows an improvement in the latency of the systolic array, which has been reduced from 1 to 0. A reduction of N+1 delay elements has been achieved for the FIR filter. An error analysis for the architecture is made.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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A New Realization for 2-D Digital Filters
G. Lampropoulos, M.M. Fahmy · 1987 · 20 citations
Engineering, Computer Engineering, Electrical Engineering +17