A 4.5 mW/Gb/s 6.4 Gb/s 22+1-Lane Source Synchronous Receiver Core With Optional Cleanup PLL in 65 nm CMOS

Abstract

This paper describes the design of a product-level low-power source-synchronous link receiver macro for data rates of 3.2-6.4 Gb/s. The receiver macro consists of 22 data channels plus one forwarded-clock channel, and supports both differential and ground termination. A pulsed CDR with programmable bandwidth is implemented to save power in the CDR. Time dithering is applied to the CDR to avoid notches in the jitter tolerance curve. The receiver clock path incorporates both a clean-up PLL and a polyphase filter for RX clock generation, from which one can be chosen to generate the receive clock. It is shown how jitter in a source-synchronous link is related to skew between clock and data, as well as cross-talk from the data to the clock wires. The jitter performance of the RX using either the polyphase filter or the PLL for clock generation is compared for different loop bandwidths. The RX core was implemented in a 65 nm Bulk CMOS technology. Total power consumption for the 22+1 lane RX PHY core running at 6.4 Gbps with the polyphase filter and in pulsed CDR mode is 635 mW or 4.5 mW/Gbps.