Embedded Active Device Packaging Technology for Next-Generation Chip-in-Substrate Package, CiSP

TLDR

Packaging technologies must evolve to meet demands for high‑density, high‑speed, high‑performance, and multifunction portable electronics, and embedding active devices into organic substrates—such as chip‑in‑substrate packages—offers improved electrical performance and system integration. The study uses DDRII memory as a CiSP test vehicle to demonstrate enhanced electrical and thermal performance and will present updated reliability test results. The authors embed 50‑µm‑thick DDRII chips into a dielectric substrate using wafer thinning, die bonding, high‑flatness lamination, and then create PCB‑compatible interconnections via laser drilling, via metallization, and patterning, followed by lead‑free reliability testing. The CiSP design yields superior electrical and thermal performance compared to conventional packaging.

Abstract

As the demands for high-density, high-speed, high-performance, and multi-function in portable electronic products, packaging technologies require significant improvement to bring out ICs' performance and shrink the total module or package size. One representative technology is to embed active devices into an organic substrate by sequential build-up processes, for example, chip-in-polymer by IZM, bumpless build-up layer by Intel, and chip-in-substrate package (CiSP) by EOL/ITRI. Through embedding the semiconductor chip in the organic substrate, the package with very good electrical performance and good capability for system integration can be realized. In this research, DDRII memory was chosen as the CiSP test vehicle, and the designed structure provides better electrical and thermal performance. Several core techniques, such as wafer thinning, die bonding, high-flatness lamination, were well developed to embed DDRII-like thin chips (50 /spl mu/m thick) into dielectric material on a carrier substrate. The PCB compatible laser drilling, via metallization, and patterning technologies were subsequently followed to form an electric path from chip-pad to outer, which provides shorter interconnection for the demand of fast electrical response application. Moreover, the vehicle was tested by lead-free reliability tests, inclusive of pre-condition (3 reflows at 260/spl deg/C), level B thermal cycle, and 168 hrs PCT tests. The newest results of the reliability tests will be presented in the paper.