A self-aligned pocket implantation (SPI) technology for 0.2- mu m dual-gate CMOS

Abstract

The self-aligned pocket implantation (SPI) technology developed features a localized pocket implantation using a gate electrode and TiSi/sub 2/ films as self-aligned masks. This process provides high punchthrough resistance and high current driving capability while suppressing the impurity concentration in the twin well. The drain junction capacitance is decreased by 30% for N-MOSFETs and by 49% for P-MOSFETs, compared to conventional LDD devices. It is found that a dual-gate CMOS device fabricated by the SPI technology achieves high circuit performance.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>