EngineeringComputer EngineeringComputer ScienceComputer NetworksInterconnection NetworksLow-power DesignCrossbar NetworksInterconnect ArchitectureInterconnect DesignPacket SwitchingRoutingRouting ArchitectureCrossbar SwitchesCrossbar SwitchingLow-latency InterconnectsNetwork-on-chip ArchitecturesPower-efficient Crossbar DesignRouting In Crossbar NetworksSwitch ArbitrationThroughput
Power efficient, low latency interconnects are increasingly important in a computing era dominated by growing core counts and diminishing power budgets. This paper proposes the use of a novel coding-based crossbar architecture to perform packet arbitration in parallel with switch traversal. The use of a lightweight exclusive-OR (XOR) coding scheme enables the productive transmission of packets, without waiting for arbitration, even under contention. For marginal cost compared to fully speculative techniques, switch arbitration latency can be hidden while eliminating power consuming misspeculations, increasing router throughput, and maintaining fairness.
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