Room Temperature Spalling of Thin Silicon Foils Using a Kerfless Technique

Abstract

An important factor for cost reduction of solar electricity is the reduction of silicon material quantity used for making a solar cell. It is well known in the PV industry that kerf losses associated with wafering are a limiting factor in the efforts to reduce material usage and some techniques have been developed to address this issue. The kerfless wafering technique described in this paper provides both things: a thin silicon layer foil while avoiding the sawing step. This technique consists of three steps: (i) dispensing a stress inducing layer on the silicon surface of a slab; (ii) thermal processing to activate the stress and detach a thin silicon layer of silicon; (iii) a chemical cleaning to obtain a flat thin foil of silicon. This technique was used with an epoxy stress inducing layer to obtain thin silicon foils, demonstrating for the first time the capability to obtain several foils out of the same substrate and using only room temperature cooling step, unlike other authors who used dipping in liquid nitrogen. The relationship between epoxy layer and foil thickness is presented, along with foils with bulk minority carrier lifetimes of 80 μs.