A 60-GHz sub-sampling frequency synthesizer using sub-harmonic injection-locked quadrature oscillators

Abstract

This paper presents a 60-GHz sub-harmonic injection-locked quadrature frequency synthesizer with subsampling operation. This allows the proposed synthesizer to achieve relatively lower in-band phase noise through the use of sub-sampling operation, as well as good out-of-band phase noise through the use of sub-harmonic injection. The proposed synthesizer has been implemented in a standard 65-nm CMOS technology. It can support all 60-GHz channels and achieves a phase noise of −115dBc/Hz at 10MHz offset. The sub-sampling operation helps reducing an integrated jitter from 12ps to 2.1ps. It consumes 20.2mW and 14mW from a 20GHz sub-sampling phase-locked loop (SS-PLL) and a quadrature injection-locked oscillator (QILO), respectively.