IEEE Journal of Solid-State Circuits · 2009 · 43 citations · 5 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureLow-power DesignMicroelectronicsCmos Circuit DesignEnergy-efficient Mobile ComputingIntegrated Circuit DesignLow-power Cache DesignProcessor Core DesignProcessor MicroarchitectureCache DesignDie DesignLow-power Cmos DesignLow-power Instruction Cache DesignLow-power MicroarchitectureLow-power Processor DesignMobile Processor DesignUltra-low-power Cmos
This paper describes a low power Intel Architecture (IA) processor specifically designed for Mobile Internet Devices (MID) with performance similar to mainstream Ultra-Mobile PCs. The design relies on high residency in a new low-power state in order to keep average power and idle power below 220 and 80 mW, respectively. The design consists of an in-order pipeline capable of issuing 2 instructions per cycle supporting 2 threads, 32 KB instruction and 24 KB data L1 caches, independent integer and floating point execution units, times86 front end execution unit, a 512 KB L2 cache and a 533 MT/s dual-mode (GTL and CMOS) front-side-bus (FSB). The design contains 47 million transistors in a die size under 25 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> manufactured in a 9-metal 45 nm CMOS process with optimized transistors for low leakage. Maximum thermal design power (TDP) consumption is measured at 2 W at 1.0 V, 90degC using a synthetic power-virus test at a frequency of 1.86 GHz.
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