Effects of silicon surface orientation on submicron CMOS devices

Abstract

Effects of Si surface orientation on small dimension NMOS and PMOS characteristics at 300K and 77K have been experimentally investigated. Carrier transport in a high electric field and hot carrier-induced degradation have been examined in detail. In scaled NMOS devices alone, a triode channel transconductance depends strongly on Si surface orientation, but a pentode transconductance does not depend on it. These behaviors are qualitatively discussed with an effective mass model and carrier transport process. The Si surface orientation dependence of hot carrier-induced degradation is found to be related to the number of interface state. Based upon these results, the optimum surface orientation for submicron CMOS devices is discussed.