TACO

Abstract

The impact of coupling capacitance on delay is usually estimated by scaling the coupling capacitances (often by a factor of 2) and modeling them as grounded. This simple approach has been shown to be overly pessimistic in some cases, while somewhat optimistic in others. This paper introduces TACO, a timing analysis methodology that produces tight bounds on worst- and best-case timing for circuits with dominant coupling capacitance. The methodology utilizes a coupled Ceff gate model for capturing the provably worst- and best-case delays as a function of the timing-window inputs to the gates.