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Defectless Monolithic Low-k/Cu Interconnects Produced by Chemically Controlled Chemical Mechanical Polishing Process with In situ End-Point-Detection Technique
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2009
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EngineeringIntegrated CircuitsThin Film Process TechnologyTan BarrierInterconnect (Integrated Circuits)Surface TechnologyChemical EngineeringWafer Scale ProcessingCmp SlurryAdvanced Packaging (Semiconductors)Electronic PackagingThin Film ProcessingMaterials ScienceMaterials EngineeringElectrical EngineeringSitu End-point-detection TechniqueChip On BoardChip AttachmentMicroelectronicsSurface CharacterizationMicrofabricationMaterials CharacterizationApplied PhysicsSurface ScienceThin FilmsSurface ProcessingLocal Cmp Apparatus
Defectless monolithic low-k/Cu interconnects have been obtained for low-power LSIs by a chemically controlled local chemical mechanical polishing (CMP) process to remove a Cu/TaN barrier on hydrophobic SiOCH low-k films. In the first step, Cu-CMP, a unique end-point-detection (EDP) method is implemented to detect a very thin Cu layer (∼100 nm) that remains on the TaN barrier by in situ white-light interferometry, which is implemented in the local CMP apparatus where the wafers undergoing polishing are oriented face-up. In the second step, TaN-CMP, a SiO2 hard-mask (HM) layer on the low-k film is selectively removed to reduce the nonuniformity of the Cu line thickness, and accordingly, those of the resistance and capacitance. Here, a CMP slurry with an oxidizer is used to change the low-k surface from a hydrophobic condition to a hydrophilic condition, improving wettability and reducing the number of scratches and abrasive particles. In the post-CMP cleaning, an alkaline rinse solution with an oxidation–reduction potential (ORP) of less than -0.5 V vs a normal hydrogen electrode (NHE) produces a clean low-k surface resulting in monolithic low-k/Cu interconnects with excellent dielectric properties comparable to those of SiO2/Cu interconnects.