A study of high-level synthesis: Promises and challenges

TLDR

FPGA platforms are widely used in domains such as networking, computer vision, and cryptography, but designing in HDLs requires effort an order of magnitude higher than using high‑level languages, prompting the use of high‑level synthesis tools that generate hardware from C/C++/SystemC descriptions and promise reduced effort without detailed platform knowledge. The authors study the AutoPilot HLS tool to assess its suitability for a variety of application domains. They used AutoPilot to generate hardware from C/C++/SystemC algorithm descriptions and evaluated its performance across multiple domains. The study provides guidelines for software design, identifies limitations of mapping general‑purpose software to hardware via HLS, and shows that for the examined applications the tool achieves 4×–126× speedups and reduces design effort by a factor of five compared to manual HDL design.

Abstract

A wide variety of application domains such as networking, computer vision, and cryptography target FPGA platforms to meet computation demand and energy consumption constraints. However, design effort for FPGA implementations in hardware description languages (HDLs) remains high - often an order of magnitude larger than design effort using high level languages (HLLs). Instead of development in HDLs, high level synthesis (HLS) tools generate hardware implementations from algorithm descriptions in HLLs such as C/C++/SystemC. HLS tools promise reduced design effort and hardware development without the detailed knowledge of the implementation platform. In this paper, we study AutoPilot, a state-of-the-art HLS tool, and examine the suitability of using HLS for a variety of application domains. Based on our study of application code not originally written for HLS, we provide guidelines for software design, limitations of mapping general purpose software to hardware using HLS, and future directions for HLS tool development. For the examined applications, we demonstrate speedup from 4X to over 126X, with a five-fold reduction in design effort vs. manual design in HDLs.