The development of heterojunction integrated injection logic

Abstract

The development of heterojunction integrated injection logic (HI/sup 2/L) since 1982 is described. The baseline process that uses AlGaAs/GaAs emitter-down HBTs (heterojunction bipolar transistors) as the switching element is presented. Two sets of design rules, one using a 7.0- mu m collector and 8.0- mu m metal pitch and another using a 5.0- mu m collector and 5.0- mu m metal pitch, have been developed for the pilot line circuit fabrication. Typical propagation delays obtained for a fan-out=4 HI/sup 2/L gate using the 7.0- and 5.0- mu m collector processes are 250 and 150 ps, respectively, at a power dissipation of 5 mW per gate. LSI and VLSI circuits as complex as 4 K-gate arrays and 32-bit MIPS microprocessors have been fabricated successfully using the HI/sup 2/L technology.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>