A 0.10 μm CMOS, 1.2 V, 2 GHz phase-locked loop with gain compensation VCO

Abstract

This paper describes a 1.2-V, 2-GHz low-jitter phase-locked loop (PLL) using a gain compensation VCO. In order to improve the jitter performance of PLLs, we have developed a new VCO that has a low gain and a linear V-f characteristic. The characteristics of our VCO are achieved by using three V-I converters and blending their different characteristics. The PLL is fabricated in 0.10-/spl mu/m CMOS technology. Its loop filter includes MOS transistors for I/O in order to suppress the influence of gate leakage current. At 1.2 V, 2-GHz operation, measured rms and peak-to-peak jitter of the PLL are 2.8 and 21 ps, respectively.