A 1 GHz single-issue 64 b PowerPC processor

TLDR

This 64‑bit single‑issue PowerPC processor, built with 19 million transistors in a 0.12 µm six‑layer copper interconnect CMOS process, targets a nominal 1 GHz clock and relies largely on delayed‑reset and self‑resetting dynamic circuit macros. The paper introduces a set of architectural enhancements, including a fully pipelined four‑stage double‑precision FPU, sum‑addressed MMUs with 64 kB two‑cycle caches, full 64‑bit PowerPC ISA support, dynamic PLA‑based control, a balanced floorplan, burn‑in‑capable delayed‑reset circuits, and improved clocking. The implementation relies on delayed‑reset dynamic macros, sum‑addressed MMUs, a dynamic PLA‑based control scheme, and a balanced floorplan to optimize critical paths and support burn‑in testing. On the fast end of the process, the chip achieves 1.15 GHz at 1.87 V, 101 °C, and 112 W.

Abstract

This 64 b single-issue PowerPC processor contains 19M transistors and is fabricated in 0.12 /spl mu/m L/sub eff/ six-layer copper interconnect CMOS. Nominal processor clock frequency is 1.0 GHz. At the fast end of the process distribution the processor reaches 1.15 GHz (1.87 V, 101/spl deg/C, 112 W). As in a previous design, nearly the entire processor is implemented using delayed-reset and self-resetting dynamic circuit macros. New contributions include: (1) a fully pipelined, four execution-stage IEEE double-precision floating-point unit (FPU) with fused multiply-add. 2) Sum-addressed memory management units (MMUs) and 64 kB 2-cycle caches. (3) Support for the full 64 b PowerPC instruction set. (4) Dynamic PLA-based control. (5) A microarchitecture and floorplan that balances critical paths. (6) Delayed-reset dynamic circuits that support stress testing (burn-in). 7) Improved clock generation and distribution.